1. Field of the Invention
This invention relates generally to mixed delay lines, and particularly to analog delay circuits and methods for setting a tuning range of the analog delay circuits.
2. Description of Related Art
In modem high frequency integrated circuits, it is often necessary to generate internal clocks with predetermined phase relationships to a reference clock. Conventionally, a Phase Locked Loop (PLL) or Delay Locked Loop (DLL) has been used to generate this predetermined phase relationship. A variety of reasons may exist for requiring the phase relationship. For example, it may be desirable to adjust an internal clock relative to a reference clock to minimize delay between the reference clock and output signals controlled by the internal clock. In another example, it may be desirable to minimize skew or eliminate delay between the reference clock and an internal clock buffered by a large internal clock tree. A PLL or DLL may be implemented to reduce or eliminate delay between the reference clock and the final branches of the internal clock tree. In yet another example, it may be desirable to create a phase splitter to generate phase-shifted clocks, for example at phase delays of 90, 180, 270, and 360 degrees relative to the reference clock. These phase delayed clocks are often used for circuits that perform different operations during different phases of the clock cycle.
DLLs are conventionally all digital, all analog, or some form of digital/analog hybrid. Digital DLLs include a delay line of digital elements with discrete delays. A phase detector compares the reference signal and a feedback signal to determine whether more discrete delays should be added to the delay line, increasing the overall delay, or discrete delay elements should be removed from the delay line, decreasing the overall delay. Digital DLLs have the advantage of a wide locking range and ability to achieve phase lock between the reference clock and feedback signal in a relatively short lock time. However, they have the disadvantage of pronounced jitter in the output clock or an undesired skew between the feedback clock and the reference clock due to the availability of only discrete time adjustments in increments of the delay through a single delay element.
Analog DLLs conventionally contain delay elements that may be adjusted by modifying a bias voltage controlling the delay elements. Similar to the digital DLL, an analog DLL includes a phase detector. However, the result of the phase comparison is a bias voltage, which may move up or down. The bias voltage controls the voltage swing of the analog delay elements and, as a result, the delay through the analog delay line. Analog DLLs have the advantage of generating a continuously variable delay, which creates smooth (i.e., continuous as opposed to discrete) clock period adjustments and relatively low phase jitter. However, Analog DLLs have a relatively narrow locking range and relatively long lock time compared to digital DLLs.
Hybrid analog/digital DLLs attempt to incorporate the advantages from both digital DLLs and analog DLLs. Hybrid DLLs may take on many alternate forms. However, hybrid DLLs may be generally considered as either a digital delay line in series with an analog delay line or an analog delay line with selectable taps at the output of each of the analog delay elements. Hybrid DLLs conventionally use the coarse digital elements to achieve an initial lock to the reference clock, while fine adjustments within the delay time of a discrete digital element may be performed by modifying the delay time through the analog delay elements.
However, analog fine adjustment may contain its own set of tuning problems. Conventionally, it has not been possible, using analog delay lines, to adjust across all operational corners of variations in Process, Voltage, Temperature, and Frequency of the output clock (PVTF). An analog delay line tends to integrate at slow comers (i.e., slow process, low voltage, high temperature) and high clock frequencies. As a result, the bias voltage must be adjusted to compensate. On the other hand, at the fastest corner (i.e., fast process, high voltage, and low temperature) and low clock frequency, the bias voltage must be adjusted in the opposite direction in order to provide adequate tuning range. If the bias voltage for the fine tuning is not set initially at a value allowing substantial tuning range in both directions, coarse digital corrections may be required introducing undesired jitter.
There is a need for a hybrid DLL using an analog delay line for fine-tuning, wherein an initiating bias voltage may be established to allow a substantial fine tuning range by adapting to differences in operational PVTF parameters. Additionally, there is a need for a means for adjusting between establishing the initiating bias signal and maintaining a bias signal responsive to changes in the reference clock in order to maintain a phase lock in the hybrid DLL.